Features to Implement- Read and write registers(Including Debug Registers, Control Registers, MSRs, Segment Descriptor Cache Registers, PCI Registers)
- Read and write memory.
- Read from and write to I/O port.
- Set Execution Breakpoints and Debug Register Breakpoints
- Able to use public advanced debug capabilities such as Debug Store, Performance Register Break, BTF (Branch Trap Flag) etc.
- (Intel-only) Set Special Breakpoints on special CPU transitions such as C6, CC1, CC3, CC6, SMM and VMX transitions
- (Intel Pentium M-only) Set Bus Breakpoints that break on certain values that appear on the FSB
- (Intel-only) Trace special events that occur in the CPU (such as MSR read/write, MWAIT)
- (Intel-only) Access the Internal Control Register Bus of the CPU
- (AMD-only) Access HyperTransport Trace Memory, which records the last few HyperTransport transactions
- (AMD-only) Access Microcode ROM, L1, L2 caches
- (AMD-only) Data Breakpoints that break data values with a configured data pattern and mask.
- (Itanium-only) Access L1 and L2 caches
- Access PCI configuration register problems even when the CPU and chipset are not configured properly
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