AMD K5 (similar to P5)
IR Register Size: 5
Boundary Scan
EXTEST: 0x0 SAMPLE/PRELOAD: 0x1 IDCODE:0x2
CLAMP: ? RUNBIST: ? BYPASS: 0x1F HIGHZ:? Debug
a possible write register at 0x23 AMD K6
departure from k5. designed by the guys at NexGen (NX686 ). I remember seeing some docs about their debugging once. AMD K7IR Register Size: 5
Boundary Scan
EXTEST: 0x0 SAMPLE/PRELOAD: 0x1 IDCODE:0x2 HIGHZ:0x3
CLAMP: 0x4 RUNBIST: 0x7 BYPASS: 0x1F
DebugMost of these functions were found in [ref here]. | BYPASS2 |
Range of BYPASS Registers |
AMD Spec. |
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| BYPASS2 |
Range of BYPASS Registers |
AMD Spec. |
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| CLKCTRL |
PLL and Clock control |
AMD Spec. |
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| RINGOSC |
Ring Oscillator |
AMD Spec. |
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| RUNATPG |
Scan Data for Debug |
AMD Spec. |
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| PGMSTPC |
Self Timed Circuits |
AMD Spec. |
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| CONFIG |
Test Mode Configuration |
AMD Spec. |
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| MANID |
Manufacturer Device ID |
AMD Spec. |
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| PLLCHZ |
PLL Characterization Test Modes |
AMD Spec. |
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| USEHDT |
Hardware Debug Tool Registers |
AMD Spec. |
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| Private |
Private Registers |
AMD Spec. |
USEHDT connects the HDT register to the JTAG scan chain. This register contains a command field, a subcommand field, a data field and status flags.
HDT functionality is available using AMD Hardware Debug Tool or Sage Engineering's SmartProbe. Soon it will be available in HardIce. | 