Instruction Name Reference
P5 MicroarchitecturePentiumIR Register Size: 13Boundary ScanEXTEST: 0x0SAMPLE/PRELOAD: 0x1 IDCODE:0x2 RUNBIST: 0x7 BYPASS: 0x3FFF HIGHZ: 0x3FFB P6 MicroarchitectureUsed in Pentium Pro, Pentium II, Pentium II Xeon, Pentium III, and Pentium III Xeon microprocessors. the following functions were noted in some p6 debug code. PMENTER: 0x2C PMNOW: 0x2B PMEND: 0x2F Read/Write: 0x22 Write Register: 0x24 Read: 0x32 It was also noted that amd k5 has an "apparently identical" implementation. One difference being a write register at 0x23 Pentium ProIR Register Size: 6Boundary ScanEXTEST: 0x0SAMPLE/PRELOAD: 0x1 IDCODE:0x2 CLAMP: 0x4 RUNBIST: 0x7 BYPASS: 0x3F HIGHZ: 0x8 Pentium 2IR Register Size: 6Boundary ScanEXTEST: 0x0SAMPLE/PRELOAD: 0x1 IDCODE:0x2 CLAMP: 0x4 RUNBIST: 0x7 BYPASS: 0x3F HIGHZ: 0x8 Pentium IIIIR Register Size: 6Boundary ScanEXTEST: 0x0SAMPLE/PRELOAD: 0x1 IDCODE:0x3 CLAMP: 0x4 RUNBIST: 0x7 BYPASS: 0x3F HIGHZ: 0x8 Pentium MIt is likely that most of the p6 functionality is here.Netburst MicroarchitectureUsed in Pentium 4, Pentium D, and some Xeon microprocessors. Commonly referred to as P7 although its internal name was P68 (P7 was used for Itanium). Later revisions were the first to feature Intel's x86-64 architecture.A short lived architecture. However, it is believed much pioneering went into processor validation. The following was "found": CRBUSGO - 0x09 Pentium 4IR Register Size: 7 Boundary ScanEXTEST: 0x0SAMPLE/PRELOAD: 0x1 IDCODE:0x2 CLAMP: 0x4 RUNBIST: 0x7 HIGHZ:0x8 BYPASS: 0x7F DebugThe following table describes the JTAG functionality on Netburst Architecture Processors. Most of the following table was first discovered in [ref here]. It is uncertain if any of these functions were available in the P6 line. It is very likely that many of these have implementations in previous processors, but not in whole as the "P4 Spec" defines. Most of this surely found its way into Intel's latest line.
Intel Xeon (Netburst-based)IR Register Size: 7 Boundary ScanEXTEST: 0x0SAMPLE/PRELOAD: 0x1 IDCODE:0x2 RUNBIST: 0x7 HIGHZ:0x8 CLAMP: 0xC BYPASS: 0x7F Itantium MicroarchitectureWho the hell uses itaniums?Intel ItaniumIR Register Size: 6 Boundary ScanEXTEST: 0x0SAMPLE/PRELOAD: 0x1 IDCODE:0x2 CLAMP: 0x4 RUNBIST: ? HIGHZ:0x8 BYPASS: 0x3F Intel Itanium CoreIR Register Size: 8 Boundary ScanEXTEST: 0x0SAMPLE/PRELOAD: 0x1 IDCODE:0x2 RUNBIST: 0x7 HIGHZ:0x8 CLAMP: 0xC BYPASS: 0xFF Core MicroarchitectureRearchitected P6-based microarchitecture used in Core 2 and Xeon microprocessors, built on a 65 nm process.Bonnell MicroarchitectureAtomNehalem MicroarchitectureReleased 2008-11-17, built on a 45 nm process and used in the Core i7, Core i5, Core i3 microprocessors.Sandy Bridge MicroarchitectureReleased 2011-01-09, built on a 32 nm process and used in the Core i7, Core i5, Core i3 second generation microprocessors. Formerly called Gesher but renamed in 2007.[1]ReferencesCodenames, dates, etchttp://titancity.com/articles/intel.htmlhttp://www.informit.com/articles/article.aspx?p=130978&seqNum=23 |
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